1. (FIELD OF THE INVENTION)
The present invention relates to a semiconductor memory which can be used in, for example, the image processing in a video tape recorder, television or the like. More specifically, the invention relates to a semiconductor memory which can be applied to an asynchronous 3-port FIFO memory.
2. (DESCRIPTION OF THE BACKGROUND ART)
Asynchronous 3-port FIFO memories, which have serial-access memories (SAM) writing and reading out data, line by line, are known. Such types of memories include first, second and third SAM's. The first SAM comprises a selector, a register which may have, for example, a capacity of 1024 bits, and a first latch circuit. The second SAM comprises a second latch circuit and a first shift register. The third SAM comprises a third latch circuit and a second shift register.
Writing clock signals CKW are supplied for the selector, the register and the first latch circuit. Serial data are supplied for the register by means of an input terminal. When clear signals CLR0 are supplied to the selector, the data are cleared to be set to 0. The selector is actuated by means of write enable signals WE. Address signals are formed when clock signals CKW are supplied for the selector. The address signals are supplied for the register by means of the selector. Serial data from the input terminal are stored in the register at predetermined locations designated by the address signals. The data stored in the register is temporarily latched by the first latch circuit.
The data latched by the first latch circuit is written, line by line, on a dynamic random-access memory (DRAM) at a predetermined location assigned by address signals produced from a writing address circuit.
The data written on the DRAM at a predetermined location assigned by address signals produced from a first read-out address circuit is read out, line by line, to be transferred to the second latch circuit to be further transferred to the first shift register. Read-out clock signals CKR 1 are supplied for the first read-out address circuit, the second latch circuit and the first shift register. Clear signals CLR 1 are also supplied for the first shift register.
The data transferred to the first shift register is shifted by 1-bit whenever the clock signals CKL 1 are outputted to a first output terminal to serve as first data.
On the other hand, the data written on the DRAM at a predetermined location assigned by address signals, which are produced from a second read-out address circuit, is read out, line by line, to be transferred to the third latch circuit to be further transferred to the second shift register. Read-out clock signals CKL 2 are supplied for the second address circuit, the third latch circuit and the second shift register. Clear signals CLR 2 are also supplied for the second shift register.
The data transferred to the second shift register is shifted by 1-bit whenever the clock signals CKL 2 are outputted to a second output terminal to serve as second data.
A first port comprises the selector, the register, and the first latch circuit. A second port comprises the second latch circuit and the first shift register. A third port comprises the third latch circuit and the second shift register. As mentioned above, the first, second and third ports can actuate asynchronously of each other.
However, in the above-mentioned device, there is a disadvantage in that size of he chips is relatively large so that cost becomes high since the area of the SAM including the register, the latch circuit and so forth is relatively large. In addition, the device does not have good operating efficiency.